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t=2033 absolutely killed the entire thing, conveniently at the very end of the video. Who would be happy with a product that needs us to manually copy and paste _p1 _p2 _p3 _p4 etc for as many parameter sweep points there are before getting the results? What year is it?

Why do people use different package size and capacitors? Is it because of the different voltage ratings?

I got an error clearances when connecting the trace to the pad. the signal of the same name enters its pad, and Altium gives an error that the clearance is less than on rule (because it is zero) and if you change the number in the rule, then it will change in the error. (if you disable the rules about clearance, the error disappears). Please, can somebody help me, has this ever happened to anyone in practice and how to deal with it?

Do you think adding a hatch pattern to a ground plane below the switch node of a switching regulator to keep a good return path but reduce unwanted capacitance is a good idea?

Collapse of the soviet union? I'd like to hear that story

I'm not sure about the IC being used but you can measure the current using the DCR of the inductor through an RC circuit in which the voltage across the capacitor will be equal to the voltage across the DCR of the inductor (some ratios related here and there), and for this type of measurement a kelvin connection is recomended :D

Nice video, really inspired me, I'm an electrical engineer and work on audio circuits. If I use an LC lowpass filter before my LDO, will the LDO get back the missing high frequency bandwidth lost with the LC filter ? also will the LDO act as a buffer so all the capacitors after the LDO won't interact with the LC filter before the LDO, right ?

But the Kelvin connections!!?!!?!!

Hmm yes, I understood some of those words.

How'd you catch the C7 disconnect? Snap grids are your friend 😆

Nice to hear from you after about 12 years :) Wishing you luck.

Thx, very interesting. Would love to talk to Greg for a day 😃!

I agree on the copper fills. Sometimes, its just hard to break the old habits practiced by seasoned pcb designers whenever we highlight on the concerns of emissions

I am interested in PCB design course basic to advanced training avelbel for you

Is there a beginner's programming tutorial for the GA144 ? That sounds like an awesome chip !

Btw, doing the routing of hi-speed-signals (including I/Os with considerable short rise/fall times) early and placing the return vias at the same time when they swith layers can reduce later problems/overhead-work to add the return vias.

Great video

Hi, Great video. Question about the the stackup. Why not PWR plane on layer 3? As you mention in the video the tight coupling between a PWR and GND layer is important at higher frequencies and in this way it would be closer to the top signal layer where the FPGA is.

PCB design is engineering and art in one package. Not everyone can do that.

I hate this

These guys change their tools every day. You cannot focus on your design anymore. You are constantly focused on learning where things are and by the time you figure it out they change it again. So frustrated

These guys change their tools every day. You cannot focus on your design anymore. You are constantly focused on learning where things are and by the time you figure it out they change it again. So frustrated

Thanks for sharing this info ! Are these the same capacitors can be used as a RC Snubber ? I dont see the ESR anywhere in the datasheet.

I dont think this video considers the ST part shown there actually has a large ground area and power area in the middle. So really 10 layers isnt needed.

Want your design reviewed by Zach? Reach out to him on LinkedIn with your design and production files for a chance to be featured on our channel: www.linkedin.com/in/zachariah-peterson/

Want your design reviewed by Zach? Reach out to him on LinkedIn with your design and production files for a chance to be featured on our channel: www.linkedin.com/in/zachariah-peterson/

Want your design reviewed by Zach? Reach out to him on LinkedIn with your design and production files for a chance to be featured on our channel: www.linkedin.com/in/zachariah-peterson/

Tune in to the FULL Interview (releasing 5/14/24): ruclips.net/video/l9mBFnner58/видео.html

I don't see why decreasing the self inductance of a trace will increase it's immunity to xtalk, I thought only the mutual inductance matters for inductive xtalk

This video provides valuable educational content, and I truly appreciate it. Thank you for sharing such helpful information. I have a question regarding impedance matching: I need to match an input impedance of approximately 1 kilohm to an output impedance of 50 ohms. Do you believe that I can achieve this using the Excel file you mentioned? Your assistance would be greatly appreciated. Thank you.

Are the PCB cut outs even needed since that looks like a 5-6mm gap so creapage and clearance is 5-6mm but also since it is under chips there are some patch unaffected so the minimal creapage is still the same as without the milled parts ?

He also did not pay attention to the fact that the contours of the board cutouts should be rounded to make it easier for the cutter to pass through

Thank you for the anti-creepage slot. I would have taken it all the way through the capacitor and optocoupler (again, standard/best practices). Regarding the silkscreen, as a final step you can modify the footprints for individual components to meet your DRC requirements. In these cases, just breaking a few lines would do.

can you tell us about how much $ were those transformers? asking mostly like how much was the core+former and how much was the coiling process since i never ordered stuff like this before.

HI Zach, I often see pcb layout recommendation saying that output cap of a psu should be placed close the output pin of the PSU. But wouldn't it be better to place an outpur cap closer to the ic's sinking power from it, to bypass series parasitic inductance?

I would have placed U8 above or underneath T1 (on the same bottom layer to reduce the length of the HV trace. The cutout in the middle, as you pointed out it's purely cosmetic. However, I would have placed a cutout around pin 8, to prevent whiskers going to the neighboring pins.

Around 9:00, is that slot in the whole board, or just in the copper layer? (It looks sort of like a slot in the whole board but _not_ the copper layer, but that doesn't make sense...) Also, if the frequencies are low enough to justify separation like that, should the connection really be close to the BVDD/BGND like that, or would it be better to do it near the top/bottom of the package?

I'm in the middle of a PoE flyback design and this video comes in very useful, thanks !

Was I misreading the drill file around 17:11? It looked like there were several hole types that differed only in size, but the difference was less than the tolerance. Is the cost of drill changes essentially nothing now? Or are manufacturers expected to optimize this on their own? Or was this just something not yet optimized? (And if so, how did they get different sizes in the first place?)

For testing the transformer you should also consider measuring the primary leakage inductance. Short out the secondary coil and measure the primary at the intended operating freq. Having too much could kill the switch if the RCD clamp isn't tuned well. There is sooo much more that could be tested here. Hope to see a video on that soon.

OnTrack logo covering information on the video all the time, annoying! Please pay attention on where you add your publicity.

Do I understand correctly that shield of usb-connector should connect to gnd directly?

This is a very important feature for me as an Altium user. I have been using this since it was first released with altium and the product has grown from unusable to nearly fully featured in less than a year. I look forward to where this product goes in the future. The biggest feature missing is scaled harness drawings. A very basic feature of harnessing software is the ability to set a bundle length and print a harness where the actual bundle length matches what you set in the harness drawing software.

If you shouldn't use a ferrite, ever... why do they exist? It could be a video: "why and how to use a ferrite?"

@Zachariah: Can you create a review on ESD/EFT/Surge Protection of small PCBs with no Frame/Chassis/Earth ground connection - with only power return or heat dissipation available for dumping the EOS?

🔹 Connect with Zach: Want your design reviewed by Zach? Reach out to him on LinkedIn with your design and production files for a chance to be featured on our channel: www.linkedin.com/in/zachariah-peterson/

🔹 Connect with Zach: Want your design reviewed by Zach? Reach out to him on LinkedIn with your design and production files for a chance to be featured on our channel: www.linkedin.com/in/zachariah-peterson/

I enjoy your reviews, how I can send you one of my designs?